www.azmicrotek.com 1630 s stapley dr, suite 127 +1 - 480- 962- 5881 mesa, az 85204 usa request a sample may 2012, rev 2.0 d escription the az100lvel16vv is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. selectable data input pairs permit switching between two different oscillator frequencies. the q hg / q hg outputs have a voltage gain several times greater than the q/ q outputs. an enable a llows continuous oscillator operation by only controlling the q hg / q hg outputs. the az100lvel16vv also provides a reference voltage (v bb ) with internal biasing resistors to each input to minimize external components. b lock d iagram f eatures ? minimizes external components ? high bandwidth for 1ghz ? similar operation as az100 lv el16v r except with selectable data input pairs ? - 147 dbc/hz typical noise floor a pplications ? dual frequency oscillators ? crystal or saw oscillators that require minimal external components. p ackage a vailability ? mlp 16 o green/rohs compliant/pb - free a z 100lvel16v v dual frequency pecl/ecl oscillator gai n stage & buffer with enable order number package marking AZ100LVEL16VRL 1 mlp 16 azm+16k 2 1 tape & reel - add 'r1' at end of pn for 7in (1k parts), 'r2' (2.5k) for 13in 2 see www.azmicrotek.com f or date code format www.azmicrotek.com
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 2 request a sample may 2012, rev 2.0 p in d escription and c onfiguration table 1 - pin description az100lvel16vtna+ pin name type function 1 d0 input data input 2 d0 input inverting data input 3 d1 input data input 4 d1 input inverting data input 5 v bb output reference v oltage 6 nc - n/a 7 v ee power negative supply 8 nc - n/a 9 en input output enable 10 q hg output high gain inverting pecl output 11 q hg output high gain pecl output 12 sel input data input select 13 v cc power positive supply 14 nc - n/a 15 q output pecl output 16 q output inverting pecl output 4 3 2 1 5 8 7 6 10 9 12 11 q nc 13 14 15 16 nc nc sel q hg q hg en v bb v ee v cc q leave pad open or connect to v ee d0 d0 d1 d1 figure 1 - pin configuration
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 3 request a sample may 2012, rev 2.0 e ng ineering n otes the data inputs are selected with the select pin (sel ). when sel is low or open (nc) data from the d0/ d0 is selected. when sel is high data from the d1/ d1 is selected. see t able 2 for data selection. the enable pin (en) works with either data input pair. when en is high or open (nc), input data is passed to both sets of outputs. when en is low, the q hg / q hg outputs will be forced low/high respectively, while input data will continue to be passed to the q/ q outputs. the en and sel inputs can be driven with an ecl/pecl signal or a full supply swing cmos type logic signal. see table 2 for enable operation. internal input biasing is accomplished with a v bb a nd separate 470 ? bias resistors connecting each data input to v bb . the v bb pin supports 1.5ma sink/sourc e current and should be bypassed to ground with a 0.01 f capacitor. each q/ q output has a 4 ma on - chip pull - down current source. external resistors may also be used to increase pull - down current of the q/ q to a maximum of 25ma each (includes a 4 ma on- chip current source). note: specifications in the ecl/pecl tables are valid when thermal equilibrium is established. table 2 - truth table en cs - sel q q q hg q hg high/open low/open d0/ d0 d0/ d0 d0/ d0 d0/ d0 high/open high d1/ d1 d1/ d1 d1/ d1 d1/ d1 low low/open d0/ d0 d0/ d0 low high low high d1/ d1 d1/ d1 low high q hg d0 en d1 sel q q q hg figure 2 - timing diagram
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 4 request a sample may 2012, rev 2.0 figure 3 - s11 figure 4 - s12 -30.00 -25.00 -20.00 -15.00 -10.00 -5.00 0.00 0.7 0.75 0.8 0.85 0.9 0.95 1 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 phase magnitude frequency (mhz) s11 mag s11 phase 50.00 75.00 100.00 125.00 150.00 175.00 200.00 225.00 250.00 0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 phase magnitude frequency (mhz) s12 mag s12 phase
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 5 request a sample may 2012, rev 2.0 figure 5 ? s 2 1 figure 6 ? s22 0.00 50.00 100.00 150.00 200.00 10 15 20 25 30 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 phase magnitude frequency (mhz) s21 mag s21 phase 0.00 5.00 10.00 15.00 20.00 25.00 30.00 0.2 0.3 0.4 0.5 0.6 0.7 0.8 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 phase magnitude frequency (mhz) s22 mag s22 phase
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 6 request a sample may 2012, rev 2.0 p erformance data table 3 ? absolute maximum ratings a bsolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic condition rating unit v cc pecl power supply v ee = 0v 0 to + 6.0 v v i pecl input voltage v ee = 0v 0 to + 6.0 v v d/d d/ d input voltage refer enced to v bb 0.75 v i out output current continuous q/ q 25 ma surge q/ q 50 continuous q hg / q hg 50 surge q hg / q hg 100 t a operating temperature range - - 40 to +85 c t stg storage temperature rang e - - 65 to +150 c esd hbm human body model electro static discharge - 2500 v esd mm machine model electro static discharge - 200 v esd cdm charged device model electro static discharge - 2000 v table 4 - 100k ecl dc characterist ics 100k ecl dc characteristics (v ee = - 3.0v to - 5.5v, v cc = gnd) symbol characteristic - 40 c 0 c 25 c 85 c unit min max min max min max min max v oh output high voltage 1 - 1045 - 835 - 1025 - 835 - 1025 - 835 - 1025 - 835 mv v ol output low voltage 1 - 1925 - 1555 - 1900 - 1620 - 1900 - 1620 - 1900 - 1620 mv v bb reference voltage - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 mv v ih input high voltage d / d - 1165 - 740 - 1165 - 740 - 1165 - 740 - 1165 - 740 mv input high voltage en , sel - 1165 v cc - 1165 v cc - 1165 v cc - 1165 v cc mv v il input low voltage d/ d - 1900 - 1475 - 1900 - 1475 - 1900 - 1475 - 1900 - 1475 mv input low voltage en, sel v ee - 1475 v ee - 1475 v ee - 1475 v ee - 1475 mv i ih in put high current en 150 150 150 150 a i il input low current en - 1 00 - 100 - 100 - 100 a i ee power supply current 1 4 7 4 7 4 7 5 1 ma 1. specified with q/ q open and each q hg / q hg output terminated through a 50 ? resistor to v cc - 2v.
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 7 request a sample may 2012, rev 2.0 table 5 - 100k lvpecl dc characteristics 100k lvpecl dc characteristics (v ee = gnd, v cc = +3.3v) symbol characteristic - 40 c 0 c 25 c 85 c unit min max min max min max min max v oh output high voltage 1,2 2255 2465 2275 2465 2275 2465 2275 2465 mv v ol output low voltage 1 ,2 1 375 1745 1400 1680 1400 1680 1400 1680 mv v bb reference voltage 1 1910 2050 1910 2050 1910 2050 1910 2050 mv v ih input high voltage d/ d 1 2135 2560 2135 2560 2135 2560 2135 2560 mv input high voltage en , sel 1 2000 v cc 2000 v cc 2000 v cc 2000 v cc mv v il input low voltage d/ d 1 1400 1825 1400 1825 1400 1825 1400 1825 mv input low voltage en , sel v ee 1825 1 v ee 1825 1 v ee 1825 1 v ee 1825 1 mv i ih input high current en 150 150 150 150 a i il input low current en 3 - 4 00 - 4 00 - 4 00 - 4 00 a i ee power supply current 47 47 47 51 ma 1. for supply voltages other that 5.0v, use the ecl table values and add supply voltage value. 2. specified with q/ q open and each q hg / q hg output terminated through a 50 ? resistor to v cc - 2v. 3. specified with en and sel forced to v ee . table 6 - 100k pecl dc characteristics 100k pecl dc characteristics (v ee = gnd, v cc = +5.0v) symbol characteristic - 40 c 0 c 25 c 85 c unit min max min max min max min max v oh output high voltage 1,2 3955 4165 3975 4165 3975 4165 3975 4165 mv v ol output low voltage 1 ,2 3075 3445 3100 3380 3100 3380 3100 3380 mv v bb reference voltage 1 3610 3750 3610 3750 3610 3750 3610 3750 mv v ih input high voltage d/ d 1 3835 4260 3835 4260 3835 4260 3835 4260 mv inpu t high voltage en , sel 1 2000 v cc 2000 v cc 2000 v cc 2000 v cc mv v il input low voltage d/ d 1 3100 3525 3100 3525 3100 3525 3100 3525 mv input low voltage en , sel v ee 3525 1 v ee 3525 1 v ee 3525 1 v ee 3525 1 mv i ih input high current en 150 150 1 50 150 a i il input low current en 3 - 1000 - 1000 - 1000 - 1000 a i ee power supply current 47 47 47 51 ma 1. for supply voltages other that 5.0v, use the ecl table values and add supply voltage value. 2. specified with q/ q open and each q hg / q hg output terminated through a 50 ? resistor to v cc - 2v. 3. specified with en and sel forced to v ee .
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 8 request a sample may 2012, rev 2.0 table 7 - a c characteristics ac characteristics (v ee = - 3.0v to - 5.5v; v cc =gnd or v ee =gnd; v cc = +3.0v to +5.5v) symbol characteristic - 40 c 0 c 25 c 85 c unit min typ max min typ max min typ max min typ max t plh /t phl propagation delay d to q / q 1 400 400 400 430 ps d to q hg / q hg 2 550 550 550 630 ps t skew duty cycle skew 3 5 20 5 20 5 20 5 20 ps vpp (ac) input sw ing 4 differential 80 1000 80 1000 80 1000 80 1000 mv single ended 150 2000 150 2000 150 2000 150 2000 mv t r /t f output rise/fall 1,2 (20% - 80%) 100 2 6 0 100 2 6 0 100 2 6 0 100 2 6 0 ps 1. specifi ed with each output terminated through a 50 ? resistor to v cc - 2v. 2. duty cycle skew is the difference between a t plh and t phl propagation delay through a device. 3. v pp is the minimum peak - to - peak input swing for which ac parameters guaranteed. the device has a voltage gain of 20 to q/ q outputs and a voltage gain of 100 to q hg / q hg outputs.
arizona microtek, inc. az100lvel 16v v dual frequency pecl/ecl oscillator gain stage & buffer with enable www.azmicrotek.com +1 - 480- 962- 5881 9 request a sample may 2012, rev 2.0 p ackage d iagram mlp 16 green/rohs compliant/pb - free msl=1 arizona microtek, inc. reserves the right to change circuitry and specifications at any time without prior notice. arizona microtek, inc. makes no warranty, representation or guarantee regarding the suitability of its prod ucts for any particular purpose, nor does arizona microtek, inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or i ncidental damages. arizona microtek, inc. does not convey any license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for a ny other application in which the failure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should buyer purchase or use arizona microtek, inc. products for any such unintended or unauthorized applica tion, buyer shall indemnify and hold arizona microtek, inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirect ly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.
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